1. Field
This disclosure relates to a multi-chip package. More particularly, this disclosure relates to a multi-chip package including sequentially stacked semiconductor chips.
2. Description of the Related Art
Generally, various semiconductor fabrication processes may be performed on a semiconductor substrate to form a plurality of semiconductor chips. In order to mount the semiconductor chips on a printed circuit board (PCB), a packaging process may be performed on the semiconductor chip to form a semiconductor package.
In order to increase storage capacity of the semiconductor package, a multi-chip package can include the sequentially stacked semiconductor chips. The multi-chip package may include a package substrate, the semiconductor chips sequentially stacked on the package substrate, a logic chip arranged on the package substrate, and conductive wires electrically connected between the semiconductor chips, the logic chip, and the package substrate.
According to related art, a bond finger may be formed on an upper surface of the package substrate outside the logic chip. Thus, the multi-chip package may have a wide width.
In contrast, in order to decrease the width of the multi-chip package, the logic chip may be arranged closely to a lowermost semiconductor chip. Therefore, a gap between the lowermost semiconductor chip and the logic chip may be narrow. However, because a molding member may not be sufficiently supplied to the narrow space, voids may be generated in the molding member.
In certain arrangements, the logic chip may be arranged in a thick die attach film interposed between a semiconductor chip and the package substrate to decrease the width of the multi-chip package. However, the thick die attach film may act as to increase a thickness of the multi-chip package.